The present invention relates to a processing apparatus that executes processing such as etching on a film structure pre-disposed on an upper surface of a substrate-like sample such as a wafer in steps of manufacturing a semiconductor device, and in particular, to a plasma processing apparatus that processes a wafer loaded and held on an upper surface of a sample stage disposed in a processing chamber inside a vacuum container, using plasma formed in the processing chamber.
With a trend to miniaturize semiconductor devices, processing accuracy has been increasing year by year which is needed for a process in which interconnects are formed by executing processing such as etching on a film structure disposed on an upper surface of a substrate-like sample such as a semiconductor wafer. To accurately perform etching using a plasma processing apparatus based on a pattern on a wafer surface, appropriately managing the temperature of a surface of a wafer during etching is important.
In recent years, there has been a demand for a technique for more quickly and precisely regulating the temperature of a wafer in each of a plurality of steps of a process for processing a wafer, in order to meet a demand for further improvement of shape accuracy. In order to control the surface temperature of a wafer in a plasma processing apparatus with the internal pressure thereof reduced to a high degree of vacuum, the following measure is conventionally taken. That is, a thermoconductive medium is introduced between a back surface of the wafer and an upper surface of a sample with the wafer loaded thereon. Thus, via the thermoconductive medium, the efficiency at which heat is transferred to the sample stage is improved and the temperature of the upper surface of the sample stage or the sample is regulated.
A general configuration of such a sample stage is such that a member defining a loading surface for a circular wafer disposed on the upper surface of the cylindrical sample stage provides the function of an electrostatic chuck. Specifically, the sample stage has a function to attract by an electrostatic force and hold a wafer loaded on the upper surface of the sample stage, on the upper surface of a film (attractive film) of a dielectric material defining the loading surface. Moreover, the sample stage allows a fluid such as He gas which promotes heat transfer to be fed to between a front surface of the loading surface and the back surface of the wafer, as a thermoconductive medium, to improve the efficiency of heat transfer between the sample stage and the wafer in the vacuum container.
Furthermore, in order to deliver and receive a wafer to and from a conveying robot that conveys the wafer from the outside of the plasma processing apparatus or unloads the wafer from the plasma processing apparatus, such a sample stage includes an arrangement that is lifted up above the loading surface of the sample stage or lowered to load the wafer onto the loading surface. As a typical such an arrangement, a plurality of pins are known which move up and down relative to the sample stage so that tips of the pins move up and down from the inside of the loading surface of the sample stage to a particular height above the upper surface. Such pins move up, and a wafer is loaded on the tips of the pins. The pins further move up above the loading surface. In this state, a wafer holding section disposed at a tip of an arm of a wafer conveying robot enters a gap formed between the back surface of the wafer and the loading surface. The wafer is then transferred from the tips of the pins onto the holding section and carried out from the plasma processing apparatus. Furthermore, in contrast, with the wafer held on the wafer holding section, the arm enters the inside of the vacuum container of the plasma processing apparatus to move the wafer on the holding section to above the tips of the pins. The wafer is transferred onto the tips of pins, and then, the arm moves out from the vacuum container.
In general, at least a particular plural number (for example, three) of such pins are housed inside through-holes that are in communication with openings positioned in the upper surface of the circular loading surface of the sample stage. The openings or the through-holes are positioned at a predetermined distance from one another around the center of the loading surface. However, the above-described arrangement for electrostatic attraction fails to be disposed inside the through-hole or opening in which each of the pins is disposed. This precludes the position where the pin is disposed from providing the function of an electrostatic attraction in the loading surface of the sample stage. At the position where the pin is disposed, the performance of heat transfer between the sample stage and the wafer may be degraded. Thus, not only may the temperature at a position of the wafer located above and corresponding to the position where the pin is disposed differs significantly from the temperature in a peripheral area but also the position where the pin is disposed may be a singularity on a temperature distribution where regulating the temperature to a desired value is difficult.
To solve such a problem, a configuration has been contemplated in which heat transfer gas such as He which is equivalent to the gas fed to between the back surface of the wafer and the upper surface of the dielectric film is fed into the through-hole or any other hole in which the pin is housed and in which the pressure of the gas with which the hole with the pin housed therein is filled is regulated to be higher than the pressure of the heat transfer gas between the wafer and the electrostatically attractive surface of the dielectric film, as in JP-A-2010-267708. This related art suppresses a decrease in the amount of heat transfer even at the position of the wafer located above and corresponding to the pin hole, thus restraining the uniformity of the in-plane-wise temperature of the wafer from being impaired.
On the other hand, the configuration in JP-A-2010-267708 includes an arrangement in which the seal between a side surface of the pin and an inner wall surface of the hole with the pin housed therein serves as an air-tight seal between the processing chamber side in the vacuum container and the inside of the sample stage. Thus, when the pins, housed in the through-hole and in the sample stage, moves up to press the tips of the pins against the back surface of the wafer to lift the wafer up above the loading surface, the pins may be damaged or the seal may be broken due to the electrostatically chucking force remaining between the wafer and the loading surface. Then, the inside of the processing chamber may fail to be maintained at the degree of vacuum suitable for processing.
To solve such a problem, JP-A-2010-153678 discloses a configuration in which each pin is peripherally enclosed and covered by a telescopic bellows below the through-hole with the pin housed therein to enable vacuum to be maintained even when the above-described damage or seal breakage may occur. JP-A-2010-153678 (corresponding to U.S. Pat. No. 8,828,257) is configured such that heat transfer gas is fed into the bellows and thus into the gap between the back surface of the wafer and the front surface of the sample stage via the hole with the pin housed therein. JP-A-2010-153678 also discloses a configuration in which the heat transfer gas is fed while the wafer is not loaded on the electrostatically attractive surface of the sample stage to suppress the entry of foreign matter into the bellows.